Field of the Invention
The present disclosure relates to integrated circuit (IC) designs and manufacturing, and more specifically to mask allocation optimization that occurs on an IC layout after decomposition.
Description of Related Art
Integrated circuit manufacturers often use a concept known as Design-For-Manufacturability (DFM), which helps keep processes consistent with features of a given manufacturing facility or foundry, to improve manufacturability. DFM defines rules specific to the foundry to help guide designers, and captures process-related sensitivity information (in an abstract or model format) that is specific to the foundry. This centers the efforts of designers to create designs that are feasible to a given foundry based on timing, area requirements, power requirements, specific design techniques used, etc.
Many yield and reliability issues that are tracked by DFM can be attributed to certain layout configurations, referred to as “process hotspots” or “hotspots,” which are susceptible to process issues such as stress and lithographic process fluctuations. It is, therefore, desirable to identify and remove these process hotspot configurations and replace them with more yield-friendly configurations.
Hotspots can be reduced by moving some shapes to alternate masks. More specifically, the process of preparing an IC design for manufacturing involves creating a layout, which shows where conductors, insulators, semiconductors, doped regions, etc., are to be located in the different layers of a multi-layer IC device. Once a layout is created, it can be decomposed into many different masks. In decomposition, IC features are separated into individual masks, such that when combined during lithography, they produce the desired features of a specific layer of the IC design.
Automated decomposition tools are capable of splitting a layout of the IC design into separate optical masks for the multiple exposures that will occur, or into separate mask phases for masks that include multiple phases. A single mask can be used to expose different mask phases using techniques (etching or other pattern of the optical mask, etc.) that create topographical changes in the underside of the mask. Therefore, for example, a single patterning layer of an IC design can be decomposed into two or more different patterns of shapes of conductors, insulators, semiconductors, etc., that are printed on two or more separate masks (or mask phases). The assignment of particular shapes to the different decomposed masks (or mask phases) of a given layer is commonly referred to as “coloring,” even though there is no actual color difference between the masks. The term coloring is used because the different masks or mask phases are shown using different colors on the display or representation. Each of the masks is then exposed on the wafer and their resulting images recombine to form the original desired pattern.
Another feature used in mask creation is optical proximity correction or optical proximity compensation (OPC), which is a technology used to compensate for different types of distortions. OPC software automatically changes the mask layout by moving segments of line edges and adding extra features that compensate the layout for distortions projected to occur during manufacturing.